Counting circuits or counters are found in numerous applications of all modern technologies. They are widely used in areas of electronics and in different fields of communication, in particular the field of telecommunication.
In particular, regarding phase difference measurements as well as frequency measurements, counters are often used as part of an overall circuit.
Basically, a counter is an arrangement for counting the number of incoming pulses of a clock signal. A counter is generally a sequential circuit which registers incoming pulses by entering, for each pulse, a new state that represents the number of pulses. The output data of the counter are the state variables.
The unit in a counter that actually registers the incoming pulses of a clock signal is referred to as the counter core. Any technology available for realizing the core of a counter sets a limit to the highest frequency that can be applied to the counter core. Besides, additional requirements on the circuit design within the chosen technology may lower this frequency limit.
The resolution accuracy of a counter is generally determined by the frequency of the clock signal that is applied thereto. A high frequency will yield a high resolution. When a counter is implemented in a given technology the frequency of the clock signal that is applied to the counter may be too high for reliable and/or optimal operation of the counter. Thus, a lower frequency has to be used, naturally leading to a lower resolution accuracy. Utilizing very high frequency technologies for realizing the counter core generally imply high effective costs for the circuit design.
FIG. 1 is a block diagram of a frequency counter in accordance with U.S. Pat. No. 5,097,490. The frequency of an input signal is counted in respect to the number of clock pulses that occur between either successive rising or falling edges of the input signal. A reference clock 31 supplies a gating circuit 30 and counter A, 34, with clock signals. The gating circuit 30 receives an input signal. Counter A, 34, receives, from the gating circuit 30, a signal that controls the period of time during which the counter A, 34, counts clock pulses. The clock signal from clock 31 is applied to an inverter 32, which provides an inverted clock signal. The inverted clock signal is supplied to another gating circuit 33 and to counter B, 35. The gating circuit 33 receives the same input signal as the gating circuit 30. Counter B, 35, receives a signal from the gating circuit 33 such that the gating circuit 33 controls the accumulation of inverted clock cycles by counter B, 35. The output signal of counter A, 34, is added to the output signal of counter B, 35, in a summing circuit 36. The total count is divided by two in a divide-by-two circuit 37.
U.S. Pat. No. 4,979,177 relates to a logic analyzer which has a counter that can reconstruct the higher resolution with which data was acquired using two phases of the logic analyzer system clock signal.
In U.S. Pat. No. 4,912,734 there is disclosed a high resolution event occurrence time counter operating in two clock domains, the domain of clock signal A and the domain of clock signal B. The two clock signals are generated from a common clock signal. Clock signal A is provided to a free running counter, preferably including a Johnson counter and a binary counter. The count data of the free running counter is stored in a counter register in response to clock signal B, and is stored in a second register as second time of arrival data upon the generation of a second signal, B SYNC. B SYNC, when generated, will clear a first register. The data of the counter register is stored in the first register as first time of arrival data upon the generation of a first signal, A SYNC. A SYNC, when generated, will clear the second register. The event occurrence time counter also includes a clock edge encoder which is responsive to an input signal and the clock signals A and B for generating the A SYNC and B SYNC signals. If the input signal arrives during the first half cycle of the common clock signal, then A SYNC is generated. If the input signal arrives during the second half cycle of the common clock signal, then B SYNC is generated. In this way the clock edge encoder controls which of first and second time of arrival data is to be provided as the output data of the circuit.
The problem of having a clock frequency that is too high for available or utilized technology, taking specific quality requirements into account, is not encountered in any of the above U.S. patents.